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Refan · 2026
Muhammad Refansa
01 — Intro

Hi, I'm Muhammad Refansa — Refan for short.

Graduation, Universitas Indonesia
02 — Education

Bachelor's in Electrical Engineering

I graduated with a focus on Electronics from Universitas Indonesia.

Soldering a small power module on the bench

From concept to circuit

What follows is what I've built.

Every project here taught me something the last one didn't.

drag me

03 — Projects

A running log of what I'm building.

Updated as new projects come together.

Tap a card to switch

Physical Design — RTL to GDSII

Verilog to GDSII, with Yosys, OpenROAD, and KLayout.

RTL TO GDSII

GCD

GCD placement — standard cells in rows

A timing violation, diagnosed and fixed — 0 violations at 2 GHz, 65% less power.

8 stages, from placement to timing analysis

TIMING CLOSURE · ECO

ibex RISC-V Core

ibex_core worst timing path highlighted on the routed layout

A real RISC-V CPU, 31.7k instances, missing timing by 15 ps across 240 paths. Traced the worst path to one undersized cell, then closed all 240 violations: 8 upsized cells and 2 pin swaps, verified in post-repair STA.

View on GitHub ↗
Black and white photo of a motorcycle helmet reflecting the street
04 — Documents

Download my documents.

My CV (English) and project portfolio (English or Korean).

Curriculum vitae

Education, training, experience and skills.

Project portfolio

Selected projects in depth, with figures.